New PDF release: Afrasian Languages

By Diakonoff, I. M.

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Thus, a main data line can "see" only one selected subdata line, which enables a reduced capacitance and thus a high speed. The hierarchical structure also confines the array area, which gives rise to disturbances, within the resultant small segment. The cell area is reduced by using self-aligned drain contacts without double-diffused drains. Metal-1 word-line strapping is used for high speed. In DINOR cells, the programming and erasing operations are opposite to those in the conventional NOR cello To erase means to set the VT of the cells to have a high value, while to program means to set the VT of the selected cell to have a low value.

An Introduction to Memory Chip Design ~. '. - . Insulator poly-SI word llne p-sub Fig. 20. 7 mm I Fig. 21. A microphotograph of the 64Mb DRAM chip in Fig. 1 The History of Memory-Cell Development An SRAM cell consists of two inverters, and two transfer MOSFETs that are connected to a pair of data (or bit) lines, as shown in Fig. 22. To achieve a flip-flop, the input and output of one inverter are connected to the output and input of the other inverter, respectively. 18, 1. 29, 1. 30]. Cells (a) and (b) are MOSFET-load cells, featuring the use of enhancement MOSFETs for cell (a) and depletion MOSFETs for cell (b).

Poly-2 power lines (VDD and Vss) are strapped at every 64 cells along the word line with metall, and each data A ~ i5L(AI) OL(AI) loeal Interconeet WL OL vss (poly- 1)(AI) (poly- 2){TiN) I I Voo (poly- 2) ' WL (poly- 1) 1- ... -- I : ! _J. - J8f ---- --, -- -- : @ , Vss (poly-2 p-well IDeal Interconeet (TIN) n-sub (b) n-well ,, , ~ AI-diHused layar contact Voo (poty- 2) (a) t A' @ T1N - dlffused layer contact l2J poly-2-diffused layer contllct poIY- l - TIN contact Fig. 26. 31]. 6 General Trends in Non-Vol&tile Memory Design and Technology 31 Fig.

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Afrasian Languages by Diakonoff, I. M.


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